>А что в компиляторе icc нет возможности явно указать под какой проц
>осуществлять сборку?

Code Generation
---------------

-x<code1>[,<code2>,...]
          generate specialized code to run exclusively on processors
          indicated by <code> as described below
            Host generate instructions for the highest instruction set and
                 processor available on the compilation host machine
            SSE2 Intel Pentium 4 and compatible Intel processors.  Enables new
                 optimizations in addition to Intel processor-specific
                 optimizations
            SSE3    Intel(R) Core(TM) processor family with Streaming SIMD
                    Extensions 3 (Intel(R) SSE3) instruction support
            SSE3_ATOM Can generate MOVBE instructions for Intel processors and
                    can optimize for the Intel(R) Atom(TM) processor.
            SSSE3   Intel(R) Core(TM)2 processor family with Supplemental
                    Streaming SIMD Extensions 3 (SSSE3)
            SSE4.1  Intel(R) 45nm Hi-k next generation Intel Core(TM)
                    microarchitecture with support for SSE4 Vectorizing
                    Compiler and Media Accelerator instructions
            SSE4.2  Can generate Intel(R) SSE4 Efficient Accelerated String
                    and Text Processing instructions supported by Intel(R)
                    Core(TM) i7 processors. Can generate Intel(R) SSE4
                    Vectorizing Compiler and Media Accelerator, Intel(R) SSSE3,
                    SSE3, SSE2, and SSE instructions and it can optimize for
                    the Intel(R) Core(TM) processor family.
            AVX     Enable Intel(R) Advanced Vector Extensions instructions

-ax<code1>[,<code2>,...]
          generate code specialized for processors specified by <codes>
          while also generating generic IA-32 instructions.
          <codes> includes one or more of the following:
            SSE2 Intel Pentium 4 and compatible Intel processors.  Enables new
                 optimizations in addition to Intel processor-specific
                 optimizations
            SSE3    Intel(R) Core(TM) processor family with Streaming SIMD
                    Extensions 3 (Intel(R) SSE3) instruction support
            SSSE3   Intel(R) Core(TM)2 processor family with Supplemental
                    Streaming SIMD Extensions 3 (SSSE3)
            SSE4.1  Intel(R) 45nm Hi-k next generation Intel Core(TM)
                    microarchitecture with support for Streaming SIMD
                    Extensions 4 (Intel(R) SSE4) Vectorizing
                    Compiler and Media Accelerator instructions
            SSE4.2  Can generate Intel(R) SSE4 Efficient Accelerated String
                    and Text Processing instructions supported by Intel(R)
                    Core(TM) i7 processors. Can generate Intel(R) SSE4
                    Vectorizing Compiler and Media Accelerator, Intel(R) SSSE3,
                    SSE3, SSE2, and SSE instructions and it can optimize for
                    the Intel(R) Core(TM) processor family.
            AVX     Enable Intel(R) Advanced Vector Extensions instructions
-mcpu=<cpu>
          same as -mtune=<cpu>
-mtune=<cpu>
          optimize for a specific <cpu>
            pentium3  - optimize for Pentium(R) III processors
            pentium4  - optimize for Pentium(R) 4 processor (DEFAULT)
-march=<cpu>
          generate code exclusively for a given <cpu>
            pentium3  - streaming SIMD extensions
            pentium4  - Pentium(R) 4 New Instructions
-msse3    generate code for Intel(R) Core(TM) Duo processors, Intel(R) Core(TM)
          Solo processors, Intel Pentium 4 and compatible Intel processors with
          Streaming SIMD Extensions 3 (Intel(R) SSE3) instruction support
-mssse3   Intel(R) Core(TM)2 processor family with Supplemental Streaming
          SIMD Extensions 3 (SSSE3)
-msse4.1  Intel(R) 45nm Hi-k next generation Intel Core(TM) microarchitecture
          with support for Streaming SIMD Extensions 4 (Intel(R) SSE4)
          Vectorizing Compiler and Media Accelerator instructions
-minstruction=<keyword>
          Refine instruction set output for the selected target processor

            [no]movbe  - Do/do not generate MOVBE instructions with SSE3_ATOM
                          (requires -xSSE3_ATOM)

-------

# ./icc -mtune=opteron
icc: command line warning #10159: invalid argument for option '-m'
# ./icc -mtune=geode
icc: command line warning #10159: invalid argument for option '-m'
# ./icc -mtune=c3
icc: command line warning #10159: invalid argument for option '-m'

Не понятно, почему не работает :)