>Слышал звон. 12.4.2. SMRAM Caching
An Intel Architecture processor supporting SMM does not unconditionally write back and inval-
idate its cache before entering SMM. Therefore, if SMRAM is in a location that is “shadowed”
by any existing system memory that is visible to the application or operating system, then it is
necessary for the system to flush the cache upon entering SMM. This may be accomplished by
asserting the FLUSH# pin at the same time as the request to enter SMM. The priorities of the
FLUSH# pin and the SMI# are such that the FLUSH# will be serviced first. To guarantee this
behavior, the processor requires that the following constraints on the interaction of SMI# and
FLUSH# be met.
In a system where the FLUSH# pin and SMI# pins are synchronous and the set up and hold times
are met, then the FLUSH# and SMI# pins may be asserted in the same clock. In asynchronous
systems, the FLUSH# pin must be asserted at least one clock before the SMI# pin to guarantee
that the FLUSH# pin is serviced first. Note that in Pentium® processor systems that use the
FLUSH# pin to write back and invalidate cache contents before entering SMM, the processor
will prefetch at least one cache line in between when the Flush Acknowledge cycle is run, and
the subsequent recognition of SMI# and the assertion of SMIACT#. It is the obligation of the
system to ensure that these lines are not cached by returning KEN# inactive to the Pentium®
processor.
12-7
SYSTEM MANAGEMENT MODE (SMM)
Intel Architecture processors do not write back or invalidate their internal caches upon leaving
SMM. For this reason, references to the SMRAM area must not be cached if any part of the
SMRAM shadows (overlays) non-SMRAM memory; that is, system DRAM or video RAM. It
is the obligation of the system to ensure that all memory references to overlapped areas are
uncached; that is, the KEN# pin is sampled inactive during all references to the SMRAM area
for the Pentium® processor. The WBINVD instruction should be used to ensure cache coherency
at the end of a cached SMM execution in systems that have a protected SMM memory region
provided by the chipset.
